The present invention relates generally to integrated circuit memory devices. More particularly, the present invention relates to memories with redundancy.
Semiconductor integrated circuit memories such as static random access memories (xe2x80x9cSRAMsxe2x80x9d) have used built-in self repair (xe2x80x9cBISRxe2x80x9d) circuits to screen for and sometimes repair certain memory failures in the factory and in the field. BISR circuits typically include a state machine, which is fabricated on the integrated circuit with the memory array for implementing a selected test algorithm. This algorithm is initiated in the factory by an external memory tester. In the field, the algorithm is initiated on start-up.
The prevailing method for detecting faults in SRAMs that have BISR circuits is to screen for these faults in the factory. In the factory, the memory and associated BISR circuit are coupled to a memory tester, which provides a supply voltage and a system clock to the memory array and provides control signals to operate the BISR circuit. Typically, memory testers use a two-pass approach through the BISR circuit test algorithm. In the first pass, memory failures are detected and repaired. In the second pass, the repairs are verified.
A common BISR test algorithm consists of several runs through the memory array. The BISR test algorithm performs a sequence of writes and reads on each cell in the memory array, comparing the output of each read with expected data. When a discrepancy is detected, the BISR test algorithm re-maps the memory addresses to replace the row containing the failing cell with a redundant row. These repairs are verified in the second pass through the BISR test algorithm. If all errors in at least some of the failing memories can be repaired by using available redundant rows, then the overall manufacturing yield for the memory devices can be increased, which reduces manufacturing costs.
When the memory is installed in the field, the BISR test algorithm is initiated on start-up. Then, during normal operation of the memory array, typical existing systems employ an address matching circuit connected to the input addresses. Incoming addresses are compared against pre-programmed failing addresses on every access cycle. If the incoming address matches a failing address, a redundant memory element is utilized in place of the target memory element. The comparison has a significant timing impact on the system. The more address bits there are, the longer it takes to perform the comparison. Currently, a 10-bit address can take 2 ns (nanoseconds) or more to be matched.
A memory device is therefore desired that has redundancy with a reduced timing penalty associated with avoiding faulty memory cells and which results in further increasing manufacturing yield as compared to existing redundancy schemes.
One embodiment of the present invention is directed to a memory array having a zone of memory elements arranged in rows and columns. Each column in the zone has a respective bit line. A plurality of bit line input-output nodes are each switchably coupled to either a respective one of the bit lines in the zone or another one of the bit lines in the zone.
Another embodiment of the present invention is directed to a method of repairing a memory array having a plurality of rows and columns, wherein each column has a respective bit line and bit line input-output node. The method includes providing a redundant column having a redundant bit line and identifying one of the columns as a defective column. The bit lines of the defective column and all columns positioned between the defective column and the first redundant column are decoupled from their respective bit line input-output nodes. The bit line input-output nodes of the defective column and the columns positioned between the defective column and the redundant column are coupled to the bit lines of the columns adjacent to the respective columns in a direction toward the redundant column. The bit line input-output node of the column positioned adjacent to the redundant column is coupled to the first redundant bit line.
Another embodiment of the present invention is directed to a memory system for replacing defective memory elements. The memory system includes a memory array having a plurality of memory elements arranged in rows and columns, wherein each column has a respective bit line and each bit line has a respective bit line input-output node. A repair circuit decouples a selected one of the bit lines from its respective bit line input-output node and shifts another of the bit lines from its respective input-output node to the input-output node of the selected bit line.